EASY TO START. BUILT TO SCALE. OPEN ACCESS FOR ALL
AGENTIC PHOTONICS DESIGN AUTOMATION PLATFORM
Supported foundry PDKs
Know the End-to-End Photonic Design Platform
Why Use PhotonForge
Photonic IC designers today juggle multiple disconnected tools across layout, device simulation, circuit analysis, and tape-out preparation. This fragmented workflow breaks continuity, forces manual hand-offs between tools, and increases the risk of costly tape-out errors. PhotonForge unifies layout, simulation, circuit analysis, foundry PDKs, and AI assistance into one platform — so your team can move from concept to fabrication-ready GDSII with less friction and fewer mistakes.
Leveraging AI to Boost Design Efficiency
AI-Powered Photonic Design in PhotonForge
FlexAgent MCP is the first physics-aware AI assistant purpose-built for photonic design workflows. Its agents operate directly on PhotonForge's serializable component schema - loading foundry PDKs, setting up and running simulations, generating chip layouts, performing DRC checks, and analyzing results - all through natural language or integrated into your IDE. It's not a chatbot bolted on. It's an engineering co-pilot wired into the platform.
Sign Up to Use PhotonForge Layout with No Cost
Why Use PhotonForge Layout
PhotonForge Layout is FREE to use. It is the same environment where you will run GPU-accelerated simulations, manage foundry PDKs, and analyze complete systems when you are ready. Start where you are. Scale when you need to.
| Capability | PhotonForge Layout | Example |
|---|---|---|
| Design model | Hierarchical, netlist-driven layout, virtual/physical connections, and connectivity built into the object model |  |
| Scripting | Python-first API fully addressable end-to-end, including routing, netlist extraction, and simulation setup |  |
| Routing | Algorithmic routing automation - S-bend, Manhattan, taper, and schematic-driven layout conversion |  |
| Verification | DRC/LVS hooks integrated into the day-to-day workflow, not a disconnected signoff step |  |
| Scalability | C++-accelerated core engine built for production-scale chip layouts |  |
| AI Readiness | AI-native by architecture - every layout operation is API-addressable, ready for agentic AI workflows today |  |